Ad7124 Namespace Reference

General namespace. More...

Enumerations
enum	BurnoutCurrent { BurnoutOff = 0, Burnout500nA, Burnout2uA, Burnout4uA }
	These bits select the magnitude of the sensor burnout detect current source. More...
enum	ClkSel { InternalClk = 0, InternalWithOutputClk, ExternalClk, ExternalDiv4Clk }
	These bits select the clock source for the ADC Either the on-chip 614.4 kHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7124 devices to be synchronized. Also, 50 Hz and 60 Hz rejection is improved when an accurate external clock drives the ADC. More...
enum	FilterType {   Sinc4Filter = 0, Sinc3Filter = 2, Sinc4FastFilter = 4, Sinc3FastFilter = 5,   PostFilter = 7 }
	Filter type select bits. These bits select the filter type. More...
enum	InputSel {   AIN0Input = 0, AIN1Input, AIN2Input, AIN3Input,   AIN4Input, AIN5Input, AIN6Input, AIN7Input,   TEMPInput = 16, AVSSInput, REFInput, DGNDInput,   AVDD6PInput, AVDD6MInput, IOVDD6PInput, IOVDD6MInput,   ALDO6PInput, ALDO6MInput, DLDO6PInput, DLDO6MInput,   V20mVPInput, V20mVMInput }
	Analog input AIN input select. More...
enum	IoutCh {   IoutCh0 = 0, IoutCh1 = 1, IoutCh2 = 4, IoutCh3 = 5,   IoutCh4 = 10, IoutCh5 = 11, IoutCh6 = 14, IoutCh7 = 15 }
	Channel select bits for the excitation current for IOUT. More...
enum	IoutCurrent {   CurrentOff = 0, Current50uA, Current100uA, Current250uA,   Current500uA, Current750uA, Current1000uA }
	These bits set the value of the excitation current for IOUT. More...
enum	OperatingMode {   ContinuousMode = 0, SingleConvMode, StandbyMode, PowerDownMode,   IdleMode, InternalOffsetCalibrationMode, InternalGainCalibrationMode, SystemOffsetCalibrationMode,   SystemGainCalibrationMode }
	Control the mode of operation for ADC. More...
enum	PgaSel {   Pga1 = 0, Pga2, Pga4, Pga8,   Pga16, Pga32, Pga64, Pga128 }
	Gain select bits. These bits select the gain to use when converting on any channels using this configuration register. More...
enum	PostFilterType { dB47PostFilter = 2, dB62PostFilter = 3, dB86PostFilter = 5, dB92PostFilter = 6 }
	Post filter type select bits. When the filter bits are set to 1, the sinc 3 filter is followed by a post filter which offers good 50 Hz and 60 Hz rejection at output data rates that have zero latency approximately. More...
enum	PowerMode { LowPower = 0, MidPower, FullPower }
	Power Mode Select These bits select the power mode. The current consumption and output data rate ranges are dependent on the power mode. More...
enum	RefSel { RefIn1 = 0, RefIn2, RefInternal, RefAVdd }
	Reference source select bits. These bits select the reference source to use when converting on any channels using this configuration register. More...

Detailed Description

General namespace.

Enumeration Type Documentation

enum Ad7124::BurnoutCurrent

These bits select the magnitude of the sensor burnout detect current source.

Enumerator
BurnoutOff	burnout current source off (default).
Burnout500nA	burnout current source on, 0.5 μA.
Burnout2uA	burnout current source on, 2 μA.
Burnout4uA	burnout current source on, 4 μA.

Definition at line 150 of file ad7124.h.

                      {
    BurnoutOff = 0, 
    Burnout500nA, 
    Burnout2uA, 
    Burnout4uA 
  };

enum Ad7124::ClkSel

These bits select the clock source for the ADC Either the on-chip 614.4 kHz clock can be used or an external clock can be used. The ability to use an external clock allows several AD7124 devices to be synchronized. Also, 50 Hz and 60 Hz rejection is improved when an accurate external clock drives the ADC.

Enumerator
InternalClk	internal 614.4 kHz clock. The internal clock is not available at the CLK pin.
InternalWithOutputClk	internal 614.4 kHz clock. This clock is available at the CLK pin.
ExternalClk	external 614.4 kHz clock.
ExternalDiv4Clk	external clock. The external clock is divided by 4 within the AD7124.

Definition at line 58 of file ad7124.h.

              {
    InternalClk = 0, 
    InternalWithOutputClk, 
    ExternalClk, 
    ExternalDiv4Clk 
  };

enum Ad7124::FilterType

Filter type select bits. These bits select the filter type.

Enumerator
Sinc4Filter	sinc4 filter (default).
Sinc3Filter	sinc 3 filter.
Sinc4FastFilter	fast settling filter using the sinc 4 filter. The sinc 4 filter is followed by an averaging block, which results in a settling time equal to the conversion time. In full power and mid power modes, averaging by 16 occurs whereas averaging by 8 occurs in low power mode.
Sinc3FastFilter	fast settling filter using the sinc 3 filter. The sinc 3 filter is followed by an averaging block, which results in a settling time equal to the conversion time. In full power and mid power modes, averaging by 16 occurs whereas averaging by 8 occurs in low power mode.
PostFilter	post filter enabled. The AD7124 includes several post filters, selectable using the POST_FILTER bits. The post filters have single cycle settling, the settling time being considerably better than a simple sinc 3 /sinc 4 filter. These filters offer excellent 50 Hz and60 Hz rejection.

Definition at line 161 of file ad7124.h.

                  {
    Sinc4Filter = 0, 
    Sinc3Filter = 2, 
    Sinc4FastFilter = 4, 
    Sinc3FastFilter = 5, 
    PostFilter = 7 
  };

enum Ad7124::InputSel

Analog input AIN input select.

Enumerator
AIN0Input	AIN0
AIN1Input	AIN1
AIN2Input	AIN2
AIN3Input	AIN3
AIN4Input	AIN4
AIN5Input	AIN5
AIN6Input	AIN6
AIN7Input	AIN7
TEMPInput	Temperature sensor (internal)
AVSSInput	AVss
REFInput	Internal reference
DGNDInput	DGND.
AVDD6PInput	(AVdd − AVss)/6+. Use in conjunction with (AVdd − AVss)/6− to monitor supply AVdd − AVss .
AVDD6MInput	(AVdd − AVss)/6−. Use in conjunction with (AVdd − AVss)/6+ to monitor supply AVdd − AVss .
IOVDD6PInput	(IOVdd − DGND)/6+. Use in conjunction with (IOVdd − DGND)/6− to monitor IOVdd − DGND.
IOVDD6MInput	(IOVdd − DGND)/6−. Use in conjunction with (IOVdd − DGND)/6+ to monitor IOVdd − DGND.
ALDO6PInput	(ALDO − AVss)/6+. Use in conjunction with (ALDO − AVss)/6− to monitor the analog LDO.
ALDO6MInput	(ALDO − AVss)/6−. Use in conjunction with (ALDO − AVss)/6+ to monitor the analog LDO.
DLDO6PInput	(DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.
DLDO6MInput	(DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.
V20mVPInput	V_20MV_P. Use in conjunction with V_20MV_M to apply a 20 mV p-p signal to the ADC.
V20mVMInput	V_20MV_M. Use in conjunction with V_20MV_P to apply a 20 mV p-p signal to the ADC.

Definition at line 95 of file ad7124.h.

                {
    AIN0Input = 0, 
    AIN1Input, 
    AIN2Input, 
    AIN3Input, 
    AIN4Input, 
    AIN5Input, 
    AIN6Input, 
    AIN7Input, 
    TEMPInput = 16, 
    AVSSInput, 
    REFInput, 
    DGNDInput, 
    AVDD6PInput, 
    AVDD6MInput, 
    IOVDD6PInput, 
    IOVDD6MInput, 
    ALDO6PInput, 
    ALDO6MInput, 
    DLDO6PInput, 
    DLDO6MInput, 
    V20mVPInput, 
    V20mVMInput 
  };

enum Ad7124::IoutCh

Channel select bits for the excitation current for IOUT.

Enumerator
IoutCh0	IOUT is available on the AIN0 pin.
IoutCh1	IOUT is available on the AIN1 pin.
IoutCh2	IOUT is available on the AIN2 pin.
IoutCh3	IOUT is available on the AIN3 pin.
IoutCh4	IOUT is available on the AIN4 pin.
IoutCh5	IOUT is available on the AIN5 pin.
IoutCh6	IOUT is available on the AIN6 pin.
IoutCh7	IOUT is available on the AIN7 pin.

Definition at line 81 of file ad7124.h.

              {
    IoutCh0 = 0, 
    IoutCh1 = 1, 
    IoutCh2 = 4, 
    IoutCh3 = 5, 
    IoutCh4 = 10, 
    IoutCh5 = 11, 
    IoutCh6 = 14, 
    IoutCh7 = 15 
  };

enum Ad7124::IoutCurrent

These bits set the value of the excitation current for IOUT.

Enumerator
CurrentOff	Off
Current50uA	50 μA
Current100uA	100 μA
Current250uA	250 μA
Current500uA	500 μA
Current750uA	750 μA
Current1000uA	1 mA

Definition at line 68 of file ad7124.h.

                   {
    CurrentOff = 0, 
    Current50uA, 
    Current100uA, 
    Current250uA, 
    Current500uA, 
    Current750uA, 
    Current1000uA 
  };

enum Ad7124::OperatingMode

Control the mode of operation for ADC.

Enumerator
ContinuousMode	Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register.
SingleConvMode	Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel.
StandbyMode	Standby mode. In standby mode, all sections of the AD7124 can be powered down except the LDOs.
PowerDownMode	Power-down mode. In power-down mode, all the AD7124 circuitry is powered down, including the current sources, power switch, burnout currents, bias voltage generator, and clock circuitry.
IdleMode	Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided.
InternalOffsetCalibrationMode	Internal zero-scale (offset) calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete.
InternalGainCalibrationMode	Internal full-scale (gain) calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration.
SystemOffsetCalibrationMode	System zero-scale (offset) calibration. Connect the system zero-scale input to the channel input pins of the selected channel. RDY goes high when the calibration is initiated and returns low when the calibration is complete.
SystemGainCalibrationMode	System full-scale (gain) calibration. Connect the system full-scale input to the channel input pins of the selected channel. RDY goes high when the calibration is initiated and returns low when the calibration is complete.

Definition at line 29 of file ad7124.h.

                     {
    ContinuousMode = 0, 
    SingleConvMode, 
    StandbyMode, 
    PowerDownMode, 
    IdleMode, 
    InternalOffsetCalibrationMode, 
    InternalGainCalibrationMode, 
    SystemOffsetCalibrationMode, 
    SystemGainCalibrationMode 
  };

enum Ad7124::PgaSel

Gain select bits. These bits select the gain to use when converting on any channels using this configuration register.

Enumerator
Pga1	Gain 1, Input Range When VREF = 2.5 V: ±2.5 V
Pga2	Gain 2, Input Range When VREF = 2.5 V: ±1.25 V
Pga4	Gain 4, Input Range When VREF = 2.5 V: ± 625 mV
Pga8	Gain 8, Input Range When VREF = 2.5 V: ±312.5 mV
Pga16	Gain 16, Input Range When VREF = 2.5 V: ±156.25 mV
Pga32	Gain 32, Input Range When VREF = 2.5 V: ±78.125 mV
Pga64	Gain 64, Input Range When VREF = 2.5 V: ±39.06 mV
Pga128	Gain 128, Input Range When VREF = 2.5 V: ±19.53 mV

Definition at line 124 of file ad7124.h.

              {
    Pga1 = 0, 
    Pga2, 
    Pga4, 
    Pga8, 
    Pga16, 
    Pga32, 
    Pga64, 
    Pga128 
  };

enum Ad7124::PostFilterType

Post filter type select bits. When the filter bits are set to 1, the sinc 3 filter is followed by a post filter which offers good 50 Hz and 60 Hz rejection at output data rates that have zero latency approximately.

Enumerator
dB47PostFilter	Rejection at 50 Hz and 60 Hz ± 1 Hz: 47 dB, Output Data Rate (SPS): 27.27 Hz
dB62PostFilter	Rejection at 50 Hz and 60 Hz ± 1 Hz: 62 dB, Output Data Rate (SPS): 25 Hz
dB86PostFilter	Rejection at 50 Hz and 60 Hz ± 1 Hz: 86 dB, Output Data Rate (SPS): 20 Hz
dB92PostFilter	Rejection at 50 Hz and 60 Hz ± 1 Hz: 92 dB, Output Data Rate (SPS): 16.7 Hz

Definition at line 174 of file ad7124.h.

                      {
    dB47PostFilter = 2, 
    dB62PostFilter = 3, 
    dB86PostFilter = 5, 
    dB92PostFilter = 6 
  };

enum Ad7124::PowerMode

Power Mode Select These bits select the power mode. The current consumption and output data rate ranges are dependent on the power mode.

Enumerator
LowPower	low power
MidPower	mid power
FullPower	full power

Definition at line 46 of file ad7124.h.

                 {
    LowPower = 0, 
    MidPower, 
    FullPower 
  };

enum Ad7124::RefSel

Reference source select bits. These bits select the reference source to use when converting on any channels using this configuration register.

Enumerator
RefIn1	REFIN1(+)/REFIN1(−).
RefIn2	REFIN2(+)/REFIN2(−).
RefInternal	internal reference.
RefAVdd	AVDD

Definition at line 140 of file ad7124.h.

              {
    RefIn1 = 0, 
    RefIn2, 
    RefInternal, 
    RefAVdd 
  };